1. M. A. Pavanello, J. A. Martino and D. Flandre, "Analog Performance and Application of Graded-Channel Fully Depleted SOI MOSFETs", Solid-State Electronics, vol. 44, n. 7, p. 1219-1222, 2000.
2. M. A. Pavanello, J. A. Martino and D. Flandre, "Graded-Channel Fully Depleted Silicon-On-Insulator nMOSFET for Reducing the Parasitic Bipolar Effects", Solid-State Electronics, vol. 44, n. 6, p. 917-922, 2000.
3. M. A. Pavanello, J. A. Martino, V. Dessard and D. Flandre, “An Asymmetric Channel SOI nMOSFET for Reducing    Parasitic Effects and Improving Output Characteristics” , Electrochemical and Solid-State Letters, vol. 1, p. 50-52, 2000.
4. M. A. Pavanello and J. A. Martino, “Extraction of the Oxide Charges at the Silicon Substrate Interface in Silicon-On-Insulator MOSFET’s”, Solid-State Electronics, vol. 43, n. 11, p. 2039-2046, 1999.
5. M. A. Pavanello, J. A. Martino and J. P. Colinge, “Analytical Modeling of the Substrate Influences on Accumulation-Mode SOI pMOSFETs at Room Temperature and at Liquid Nitrogen Temperature”, Solid-State Electronics, vol. 41, n. 9, p. 1241, 1997.
6. M. A. Pavanello, J. A. Martino and J. P. Colinge, “Analytical Modeling of the Substrate Effect on Accumulation-Mode SOI pMOSFETs at Room Temperature and at 77K”, Microelectronic Engineering, vol. 36, p. 375, 1997.
7. M. A. Pavanello, J. A. Martino and J.P. Colinge, “Substrate Influences on Fully Depleted Enhancement Mode SOI MOSFETs at Room Temperature and at 77K”, Solid-State Eletronics, vol. 41, n. 1, p. 111, 1997.

2. Papers in Conferences

1. M. A. Pavanello, J. A. Martino and D. Flandre, "Parasitic Bipolar Effects in Graded-Channel Fully-Depleted Silicon-On-Insulator nMOSFETs", Proceedings of XV SBMicro - International Conference on Microeletronics and Packaging, Manaus, p. 97-102, 2000.
2. M. A. Pavanello, J. A. Martino and D. Flandre, "Comparison of Analog Performance in Conventional and Graded-Channel Fully-Depleted SOI MOSFETs", Proceedings of XV SBMicro - International Conference on Microeletronics and Packaging, Manaus, p. 67-71, 2000.
3. M. A. Pavanello, A. S. Nicolett and J. A. Martino, "Effective Channel Length and Series Resistance Extraction Error Induced by the Substrate in Enhancement-Mode SOI nMOSFETs", 1st IEEE Latin American Test Workshop, Rio de Janeiro, p. 274-278, 2000.
4. M. A. Pavanello, J. A. Martino and D. Flandre, "Comparison of Floating-Body Effects in Conventional and Graded-Channel Fully-Depleted Silicon-On-Insulator nMOSFETs", 3rd IEEE International Caracas Conference on Devices, Circuits and Systems (ICCDCS) Technical Digest, Cancún, paper D44 - CD ROM, 2000.
5. M. A. Pavanello, J. A. Martino, V. Dessard and D. Flandre, "The Graded-Channel SOI NMOSFET and Its Potential to Analog Applications", ICMP99 - International Conference on Microeletronics and Packaging Technical Digest, Campinas, p. 105-109, 1999.
6. M. A. Pavanello and J. A. Martino, "Extraction of the Interface Charge Density at the Silicon Substrate Interface in SOI MOSFET's at Cryogenic Temperatures", ICMP99 - International Conference on Microeletronics and Packaging Technical Digest, Campinas, p. 115-120, 1999.
7. L. M. Camillo, M. A. Pavanello and J. A. Martino, "Proposal of an Inprovement in the SOISPICE Circuit Simulator", ICMP99 - International Conference on Microeletronics and Packaging Technical Digest, Campinas, p. 309-311, 1999.
8. M. A. Pavanello, J. A. Martino, V. Dessard and D. Flandre "The Graded-Channel SOI MOSFET to Alleviate the Parasitic Bipolar Effects and Improve the Output Characteristics" 9^th SOI Symposium, Electrochemical Society Proceedings, Seattle, Vol. 99-3, p. 426, 1999.
9. M. A. Pavanello and J. A. Martino, "Extraction of the Oxide Charges at the Buried Oxide/Silicon Substrate interface in Accumulation-Mode SOI pMOSFETs at Low Temperatures" 9^th SOI Symposium, Electrochemical Society Proceedings, Seattle, Vol. 99-3, p. 201, 1999.
10. M. A. Pavanello and J. A. Martino, "Effect of the Substrate Potential Drop in Accumulation-Mode SOI pMOSFETs Subthreshold Slope", ICMP98 - International Conference on Microelectronics and Packaging, Curitiba, p. 549, August, 1998.
11. M. A. Pavanello and J. A. Martino, "A New Method to Extract the Effective Trap Density at the Buried Oxide/Underlying Substrate Interface in Enhancement-Mode SOI MOSFETs at Low Temperatures", III European Workshop on Low Temperature Electronics, San Miniato, p. Pr3-45, June, 1998.
12. M. A. Pavanello, A. S. Nicolett and J. A. Martino, "Analysis of the Susbstrate Effect on Enhancement-Mode SOI nMOSFET Effective Channel Length and Series Resistance Extraction at 77 K", III European Workshop on Low Temperature Electronics, San Miniato, p. Pr3-49, June, 1998.
13. M. A. Pavanello and J. A. Martino, "A New Method For Determination of The Fixed Charge Density at the Buried Oxide/Underlying Substrate Interface in SOI MOSFETs", VIII SOI Symposium da 192^nd Electrochemical Society Meeting, Paris, p. 162-167, September, 1997.
14. M. A. Pavanello, J. A. Martino and J. P. Colinge, "Analytical Modeling of the Substrate Effect on Accumulation-Mode SOI pMOSFETs at Room Temperature and at 77 K", 10^th Biennial Conference on Insulating Films on Semiconductors, Göteborg, p. 375-378, June, 1997.
15. M. A. Pavanello, J. A. Martino e J. P. Colinge, "Theoretical and Experimental Study of the Substrate Effect on Fully Depleted SOI MOSFET at Low Temperatures", II European Workshop on Low Temperature Electronics, Leuven, p. C3-67, June, 1996.

1. J. A. Martino and M. A. Pavanello, "A New Method for Determination of the Fixed Charge Density at the Buried Oxide/Underlying Substrate in Accumulation-Mode P-Channel SOI MOSFETs", Anais do XII Congresso da Sociedade Brasileira de Microeletrônica (CD ROM), Caxambu - MG, Julho, 1997.
2. M. A. Pavanello and J. A. Martino, "A New SOI MOSFET Structure to reduce the Parasitic Bipolar Effect in SOI MOSFETs", Anais do XII Congresso da Sociedade Brasileira de Microeletrônica (CD ROM), Caxambu - MG, Julho, 1997.
3. M. A. Pavanello, A. S. Nicolett and J. A. Martino, "Influence of the Substrate Effect on the Series Resistance and Effective Channel Length Extraction", Anais do XII Congresso da Sociedade Brasileira de Microeletrônica (CD ROM), Caxambu - MG, Julho, 1997.
4. M. A. Pavanello, J. A. Martino and J. P. Colinge, "Theoretical and Experimental Analysis of the Substrate Effect on Accumulation Mode P-Channel SOI MOSFET at Room and at Liquid Nitrogen Temperature", Anais do XI Congresso da Sociedade Brasileira de Microeletrônica, Águas de Lindóia - SP, p. 315, Julho, 1996.
5. J. A. Martino and M. A. Pavanello, "New Method for Determination of the Fixed Charge Densities at the Buried Oxide Interfaces in SOI MOSFETs", Anais do XI Congresso da Sociedade Brasileira de Microeletrônica, Águas de Lindóia - SP, p. 327, Julho, 1996.
6. M. A. Pavanello e J. A. Martino, "Anomalia na Tensão de Limiar de Transistores SOI MOSFET Induzida Pelo Efeito do Substrato em Baixa Temperatura", Anais do II Seminário Brasileiro de caracterização em Microeletrônica, Curitiba - PR, p. 40, dezembro, 1995.
7. M. A. Pavanello and J. A. Martino, "The Influence of the Substrate Potential Drop on Fully Depleted SOI-MOSFET Threshold Voltage at 77 K", Anais do X Congresso da Sociedade Brasileira de Microeletrônica, Canela - RS, p. 537, agosto, 1995.
8. M. A. Pavanello and J. A. Martino, "Impact of Substrate Effect on the Fully Depleted SOI-MOSFET Subtheshold Slope at 300 K and 77 K", Anais do X Congresso da Sociedade Brasileira de Microeletrônica, Canela - RS, p.527, agosto, 1995.
9. M. A. Pavanello, J. A. Martino, "Modelamento Analítico para a Queda de Pontencial no Subtrato de SOI-MOSFET", Anais do IX Congresso da Sociedade Brasileira de Microeletrônica, Rio de Janeiro - RJ, p. 546, agosto, 1994.